1. Field of the Invention
The present invention relates to a semiconductor device test method. More particularly, the invention relates to a test system employing a test controller compressing data, a data compressing circuit, and a test method.
2. Description of the Related Art
The overall increase in the operating speed of contemporary semiconductor devices mandate the use during testing of high speed test equipment (hereafter generically referred to as a “tester”). However, high speed testers are expensive, and so equivalent low speed methods testing have been developed. One such method converts high-speed serial data into parallel data for testing of semiconductor devices. In order to implement this type of test method, a tester must allocate to various data channels a required number of parallel data bits. Accordingly, the number of tester channels is limited and the corresponding number of semiconductor devices that can be simultaneously tested is considerably reduced.
Alternately or additionally, data compressing apparatuses are used to compress a parallel stream of data bits. A multiple input signature register (MISR) is widely used as the data compressing apparatus. The MISR compresses parallel data bits to generate a signature signal. The MISR generally includes a feedback tap. When a specific bit of the parallel data bits has an error, the signature signal is masked.
When a specific bit and the following bit have errors, that is, when two consecutive bits have errors, the MISR may generate a signature signal identical to the signature signal generated by compressing normal parallel data bits. This is referred to as “an aliasing effect.” In this case, the MISR has a problem in that the output signature signal indicates that two bits of parallel data bits do not have an error when in fact they do.
Accordingly, if defective bits of parallel data bits are immediately monitored in a data compressing process using MISR, the aliasing effect can be prevented. Furthermore, if high-speed serial data bits output from a semiconductor device are converted into parallel data bits, the parallel data bits are compressed into a 1-bit signature signal, and the semiconductor device is tested using the 1-bit signature signal, the semiconductor device can be tested using a tester operating at a low speed without increasing the number of tester channels.